1. Field of the Invention
The present invention relates to a semiconductor device. In particular, it relates to an array configuration of a group of bump electrodes for external connection on a flip-chip LSI (hereafter referred to as a FCLSI) having a group of bump electrodes for external connection on the surface of a semiconductor chip, or an array structure of a group of external connection terminals of a ball grid array LSI (hereafter referred to as a BGA) comprising a group of bump-shaped external connection terminals on one surface of a package.
2. Description of the Prior Art
As the scale and density of LSI increases, conventional systems configured with a plurality of LSI devices may now be integrated on one semiconductor chip. Specifically, in LSI used for communication systems, since signal processing of a plurality of channels on one chip has become possible, the number of signal lines drawn out of one chip, that is, the number of electrodes for external connection can be increased dramatically. Meanwhile, further miniaturization is required for LSI applied to mobile equipment, such as personal handy phones, thus the FCLSI or BGA is proposed, where the external connect terminals are arrayed two-dimensionally in order to achieve, multiple terminals and miniaturization, and the terminal array pitch is narrowed, as well as ingenuity has effected the layout method, this is accompanied by a further increase of the number of terminals.
For example, in Japanese Patent Application Laid-Open No. Hei 5-62978 (hereafter referred to as the well-known example), a flip chip, wherein layout density is increased while maintaining distance between bumps by arranging the bumps in a staggered pattern with the same pitch throughout, is mentioned.
However, in the conventional FCLSI and BGA, for example, since a simple grid array or a staggered grid array such as that in the well-known example is adopted for all external connect terminals, although LSI may be accomplished, a new problem for mounting the LSI in practical use occurs when the array pitch becomes narrow. In other words, when the LSI where the external connect terminals are arrayed two-dimensionally, either in a simple grid array or a staggered grid array, on a printed wiring board (hereafter referred to as PWB), it becomes difficult to connect to the signal terminals at any distance more than two rows away from the outermost periphery. FIG. 20 is a diagram for illustrating this problem; FIG. 20A is a typical plane view of a PWB 930 mounting surface, on which electronic components including the conventional LSI 900 are mounted; and FIG. 20B is a typical plane view of the enlarged P section shown in FIG. 20A. For example, in FCLSI or BGA with the narrowest bump array pitch, the number of wires capable of passing through the connection electrodes corresponding to each external connect terminal of the LSI formed on a PWB used for mounting, is limited (normally to one). Consequently, when the number of wires capable of passing through the connection electrodes is, for example, one as shown in FIG. 20, all feeder wires 935 for regions outside the LSI mounting section 900P, can be formed with one wiring layer for the connection electrodes 957, which connect the signal terminals accommodated within the region containing the two rows adjacent to the outermost periphery, however, in order to draw the signal terminals out of an LSI area containing more than two rows inside of the outermost periphery, for that reason alone, it is necessary to make the PWB multi-layered, thereby leading to increased PWB costs.
In addition, it is common for FCLSI to have arranged in it an input/output buffer circuitry (hereafter referred to as I/O circuitry) for giving and receiving signals to and from the external connect terminals along the edge of the chip and to rewire the spaces between the I/O circuitry and the external connect terminals on the chip. However, since the wiring on the chip has cross sectional area that is significantly smaller than that of the wiring on the PWB on which the chip is mounted, there are problems such as a voltage drop occurring due to the wiring between the I/O circuitry and the power supply terminal, which supplies power to the circuitry, and the size of voltage drop becomes larger in proportion to the wiring length.
1. Objectives of the Invention
The objective of the present invention is to provide LSI having external connect terminals, such as bump electrodes, which are arrayed two-dimensionally on the same surface; wherein the LSI comprises a layout of external connect terminals capable of easily accommodating the feeder interconnects drawn out of the LSI mounting area from signal connection electrodes, which connect the external connect signal terminals of the LSI, with a single wiring layer in the PWB on which the LSI is mounted, even if the number of signal terminals are increased.
2. Summary of the Invention
A semiconductor device of the present invention comprises a plurality of bump electrodes for external connection arrayed two-dimensionally on the surface of a rectangular- or square-shaped semiconductor chip where the desired elements and wirings are formed; wherein when directions of two edges of the chip orthogonal to each other are specified as X and Y directions, all of the bump electrodes are arranged at either of the grid points determined with a distance Sx1 between grids in the X direction and a distance Sy1 between grids in the Y direction, and the bump electrodes include a first group of bump electrodes, a second group of bump electrodes arrayed at the outer periphery of the first group of bump electrodes, and a third group of bump electrodes arrayed at the outer periphery of the second group of bump electrodes, wherein the first group of bump electrodes and the second group of bump electrodes are arrayed like a grid with an array interval distance Sx1 in the X direction and an array interval distance Sy1 in the Y direction, and the third group of bump electrodes has a structure satisfying Sx2 greater than Sx1 and Sy2 greater than Sy1, when an array interval distance in the X direction of the third group of bump electrodes arranged in the first area, which is enclosed by edges, which are parallel to a diagonal line of the chip and the X direction, is specified as Sx2, and an array interval distance in the Y direction of the third group of bump electrodes arranged in the second area, which is enclosed by edges, which are parallel to a diagonal line of the chip and the Y direction, is specified as Sy2.